Such methods and the corresponding converters are known, for example, from the D. Boettle et al article "Alcatel ATM Switch Fabric and Its Properties", Electrical Communications, Volume 64, No. 2/3, 1990, pp. 156-165, particularly FIG. 7 with its respective description. The depiction is of a combined space and time coupling element from the switching technology. It has 32 serial inputs and 32 serial outputs. Each input data stream and each output data stream is composed of several individually time-division multiplexed data streams, between which switching can take place in any way. In the example, the data streams are asynchronously combined into an ATM (Asynchronous Transfer Mode) data stream. Comparable coupling elements for synchronously multiplexed STM (Synchronous Transfer Mode) data streams are also present. The switching takes place in that all input data streams are combined by a multiplexer into a supermultiplexed data stream, are input into a central memory, are read from the central memory in a different sequence, and form a second supermultiplexed data stream, which is then distributed by a demultiplexer to the individual outputs.
For various reasons, the supermultiplexed data stream is in parallel form in the cited article and also in other examples. One reason is the reduced processing speed with parallel processing. Another reason is that when corresponding pans of the data stream, such as data words in the STM, or cells or at least larger pans of cells in the ATM, are stored in the central memory, they must be stored together, for which parallel processing is available.
The solution of the example has an intermediate step on the input and the output side, where the data streams are present in a parallel form, but not yet or no longer as supermultiplexed data streams. These intermediate steps inevitably contain a large number of lines, which however can only operate at a clearly reduced transmission speed. Basically, the possibility to change the conversion sequence exists, so that a serial supermultiplexed data stream is used as the intermediate step. However, it would then have a very high transmission speed, which is usually not possible with this technology.
The present invention provides help with the method and converters used to perform such data conversions. In particular, it is directed to a method of converting a parallel, time-division-multiplexed data stream into individual serial data streams, wherein the individual parallel data words are written in parallel into and read serially from one of a plurality of buffers, characterized in that each parallel data word is presented simultaneously to the parallel inputs of all buffers, and that for each data word, the inputs of only one buffer are enabled. It is also directed to a converter for converting a parallel, time-division-multiplexed data stream into individual serial data streams, comprising one buffer per serial data stream which can be written into in parallel and read from serially, characterized in that all buffers are connected in parallel at the input end, that the inputs of each buffer can be enabled, and that a decoding device is provided on the parallel side having means for enabling one of the buffers at a time.
Therein demultiplexers and parallel-serial converters are constructed together, so that demultiplexing and parallel-serial converting are performed in a single process. The same applies if the processes are reversed.
A particularly advantageous version results from the use of specially configured write-read memories, so-called application-specific RAM's. Memories with separate inputs and outputs (Dual-port RAM's) are used in this instance. The entire memory is subdivided into individually activatable sectors. Compared to other storage elements such as flip-flops, a RAM memory cell has a very simple structure. Compared to conventionally constructed (two-stage) converters, an entire converter according to the invention needs only about 20% of the otherwise required chip surface. Even so, there is a fairly large savings when the memories are duplicated for asynchronous operation and, in the well known manner, are alternately written into one and read out from another.